Since 1987 – Covering the Fastest Computers in the World and the People Who Run Them
Since 1987 – Covering the Fastest Computers in the World and the People Who Run Them
August 30, 2022
In this regular feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here.
A parallel algorithm for unilateral contact problems
A multidisciplinary team of Spanish researchers from the Barcelona Supercomputing Center, the Technical University of Catalonia, and the International Center for Numerical Methods in Engineering developed a parallel contact algorithm designed for high performance computing with a specific focus on its “computational implementation in a multiphysics finite element code.” Researchers based the algorithm on “the method of partial Dirichlet-Neumann boundary conditions.” It can “solve numerically a nonlinear contact problem between rigid and deformable bodies in a whole parallel framework.” Spanish researchers validated the algorithm by conducting benchmark tests and comparing the “proposed solution against theoretical and other numerical solutions.” For the benchmark tests, researchers used the MareNostrum4 supercomputer at BSC to conduct the simulations. They also “evaluated the parallel performance of the proposed algorithm in a real impact test to show its capabilities for large-scale applications.”
Authors: G. Guillameta, M. Riveroa, M. Zavala-Ake´, M. Vazquez, G. Houzeauxa, and S. Ollerb
Tensor network quantum virtual machine for simulating quantum circuits at Exascale
In this paper from a team of researchers from the Oak Ridge National Laboratory and Nvidia Corp., the authors introduce “a general tensor network based quantum circuit simulator capable of modeling both ideal and noisy quantum circuits as well as computing various experimentally accessible properties depending on the tensor network formalism used.” The new Tensor Network Quantum Virtual Machine (TNQVM) “serves as the quantum circuit simulation backend in the eXtreme-scale ACCelerator (XACC) framework.” Researchers based the version “on the scalable tensor network processing library ExaTN (Exascale Tensor Networks).” The paper details the initial benchmarks of the “framework, which include a demonstration of the distributed execution, incorporation of quantum decoherence models, and simulation of the random quantum circuits used for the certification of quantum supremacy on Google’s Sycamore superconducting architecture.”
Authors: Thien Nguyen, Dmitry Lyakh, Eugene Dumitrescu, David Clark, Jeff Larkin, and Alexander McCaskey
Optimized SWAP networks with equivalent circuit averaging for QAOA
A multidisciplinary team of researchers from the University of California at Berkeley, the Lawrence Berkeley National Lab in California, Super.tech, a division of ColdQuanta in Illinois, and the University of Chicago, present two techniques to streamline the execution of SWAP networks for Quantum Approximate Optimization Algorithm (QAOA). A SWAP network is a qubit routing sequence used to executive the QAOA efficiently. The researcher’s “techniques are experimentally validated at the Advanced Quantum Testbed through the execution of QAOA circuits for finding the ground state of two- and four-node Sherrington-Kirkpatrick spin-glass models with various randomly sampled parameters.” Results showed “a ∼60% average reduction in error (total variation distance) for QAOA of depth p = 1 on four transmon qubits on a superconducting quantum processor.”
Authors: Akel Hashim, Rich Rines, Victory Omole, Ravi K. Naik, John M.Kreikebaum, David I. Santiago, Frederic T. Chong, Irfan Siddiqi, and Pranav Gokhale
Design and implementation of ShenWei Universal C/C++
Chinese researchers from Tsinghua University introduce ShenWei Universal C/C++(SWUC), which “ is a language extension for C/C++ [developed] to better support heterogeneous programming on ShenWei many-core processors.” The ShenWei many-core series processors (which now have SW26010 and SW26010pro) provide the necessary computing power the Sunway supercomputer needs. The language reduces the engineer’s efforts and SWUC “enables fluent programming across the boundary of Management Processing Element (MPE) and Compute Processing Element (CPE).” Researchers demonstrate that “through the use of several new attributes and compiler directives, users are able to write codes running on MPE and CPE in a single file.” In addition, SWUC enables the use of “Athread library interfaces available, easing the learning curve for original ShenWei users.”
Authors: Huanqi Cao and Jiajie Chen
Stable parallel training of Wasserstein Conditional Generative Adversarial Neural Networks
Researchers from the Oak Ridge National Laboratory in Tennessee develop a “stable, parallel approach to train Wasserstein Conditional Generative Adversarial Neural Networks (W-CGANs) under the constraint of a fixed computational budget.” Their proposed approach “avoids inter-process communications, reduces the risk of mode collapse and enhances scalability by using multiple generators, each one of them concurrently trained on a single data label.” Numerical experiments and scalability tests were performed on the Summit supercomputer at the Oak Ridge Leadership Computing Facility. The researchers’ “use of the Wasserstein metric also reduces the risk of cycling by stabilizing the training of each generator.” Using the CIFAR10, CIFAR100, and ImageNet1k standard benchmark image datasets, the researchers were able to retain the “original resolution of the images for each dataset.
Authors: Massimiliano Lupo Pasini and Junqi Yin
Next generation computational tools for the modeling and design of particle accelerators at exascale
In this paper, researchers from Lawrence Berkeley National Laboratory (LBNL) detail three computation tools used for “the modeling and design of particle accelerators, readying codes up for next generation machines in the Exascale era.” First is the open source software toolkit Beam pLasma Accelerator Simulation Toolkit (BLAST) developed by LBNL researchers, which “provides modeling tools to model hybrid accelerators, containing both plasma and conventional beamline elements.” Second, ABLASTR “is a modern C++17 library used to share particle-in-cell routines between simulation codes.” Lastly, ImpactX was “developed to succeed IMPACT-Z as a new, s-based beam dynamics code with intrinsic GPU, mesh-refinement and tight coupling to time based codes and AI/ML capabilities.” Still in its early stages, ImpactX can already “model significantly larger particle ensembles than its predecessor codes,” the researchers conclude. Further developments are planned.
Authors: Axel Huebl, Remi Lehe, Chad E. Mitchell, Ji Qiang, Robert D. Ryne, Ryan T. Sandberg, and Jean-Luc Vay
Quantum algorithm implementations for beginners
Los Alamos National Laboratory researchers “review the principles of quantum programming, which are quite different from classical programming, with straightforward algebra that makes understanding of the underlying fascinating quantum mechanical principles optional.” In this paper, the authors provide an “introduction to quantum computing algorithms and their implementation on real quantum hardware.” They summarize 20 quantum algorithms with an overview on how to implement on IBM’s quantum computer, and then they examine the results of the “implementation with respect to differences between the simulator and the actual hardware runs.” The code is publicly available on GitHub at https://github.com/lanl/quantum_algorithms.
Authors: Abhijith J., Adetokunbo Adedoyin, John Ambrosiano, Petr Anisimov, William Casper, Gopinath Chennupati, Carleton Coffrin, Hristo Djidjev, David Gunter, Satish Karra, Nathan Lemons, Shizeng Lin, Alexander Malyzhenkov, David Mascarenas, Susan Mniszewski, Balu Nadiga, Daniel O’malley, Diane Oyen, Scott Pakin, Lakshman Prasad, Randy Roberts, Phillip Romero, Nandakishore Santhi, Nikolai Sinitsyn, Pieter J. Swart, James G. Wendelberger, Boram Yoon, Richard Zamora, Wei Zhu, Stephan Eidenbenz, Andreas Bärtschi, Patrick J. Coles, Marc Vuffray, and Andrey Y. Lokhov
Do you know about research that should be included in next month’s list? If so, send us an email at [email protected]. We look forward to hearing from you.
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August 30, 2022
In this regular feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…
August 30, 2022
It is perhaps not surprising that the big cloud providers – a poor term really – have jumped into quantum computing. Amazon, Microsoft Azure, Google, and their like have steadily transformed into major technology dev Read more…
August 25, 2022
Some chip pioneers from the 1980s are raising the ante in modern chip design with new opportunities provided by artificial intelligence and the open-source RISC-V architecture. Untether AI, which was co-founded by an analog and mixed signal chip pioneer Martin Snelgrove, released a new AI inferencing chip called Boqueria, which has more than 1,400 optimized RISC-V processors. That chip will compete… Read more…
August 25, 2022
Groq has deconstructed the conventional CPU, and designed its chip in which software takes over control of the chip. The Groq Tensor Streaming Processor Architecture follows a growing trend of software controlling system functions, which has happened in autonomous cars, networking and other hardware. The architecture hands over hardware controls of the chip to the compiler. The chip has integrated… Read more…
August 24, 2022
Fresh from finalizing its acquisitions of FPGA provider Xilinx (Feb. 2022) and DPU provider Pensando (May 2022) ), AMD previewed what it calls a 400 Gig Adaptive smartNIC SOC yesterday at Hot Chips. It is another contender in the increasingly crowded and blurry smartNIC/DPU space where distinguishing between the two isn’t always easy. The motivation for these device types, presented by Jaideep Dastidar… Read more…
In April 2021, Italian race car manufacturer Dallara Automobili (Dallara) needed more high-performance computing (HPC) for simulation and testing than what was available in its on-premises environment. Read more…
Financial services organizations have large volumes of customer data that includes account balances, payment transactions and information such as customer FICO scores, and credit history. Read more…
August 24, 2022
Intel has been hyping up its media delivery and cloud gaming GPUs codenamed Arctic Sound-M, and has given a formal name: Flex Series GPUs. The Flex Series GPUs will sit in the cloud datacenters for AI inferencing and graphics – such as gaming and video – to remote devices. Intel’s Vision conference in May was the coming-out party for the GPUs. Intel hasn’t provided a clear shipment date for the Flex GPUs… Read more…
August 30, 2022
It is perhaps not surprising that the big cloud providers – a poor term really – have jumped into quantum computing. Amazon, Microsoft Azure, Google, and th Read more…
August 25, 2022
Some chip pioneers from the 1980s are raising the ante in modern chip design with new opportunities provided by artificial intelligence and the open-source RISC-V architecture. Untether AI, which was co-founded by an analog and mixed signal chip pioneer Martin Snelgrove, released a new AI inferencing chip called Boqueria, which has more than 1,400 optimized RISC-V processors. That chip will compete… Read more…
August 25, 2022
Groq has deconstructed the conventional CPU, and designed its chip in which software takes over control of the chip. The Groq Tensor Streaming Processor Architecture follows a growing trend of software controlling system functions, which has happened in autonomous cars, networking and other hardware. The architecture hands over hardware controls of the chip to the compiler. The chip has integrated… Read more…
August 24, 2022
Fresh from finalizing its acquisitions of FPGA provider Xilinx (Feb. 2022) and DPU provider Pensando (May 2022) ), AMD previewed what it calls a 400 Gig Adaptive smartNIC SOC yesterday at Hot Chips. It is another contender in the increasingly crowded and blurry smartNIC/DPU space where distinguishing between the two isn’t always easy. The motivation for these device types, presented by Jaideep Dastidar… Read more…
August 24, 2022
Intel has been hyping up its media delivery and cloud gaming GPUs codenamed Arctic Sound-M, and has given a formal name: Flex Series GPUs. The Flex Series GPUs will sit in the cloud datacenters for AI inferencing and graphics – such as gaming and video – to remote devices. Intel’s Vision conference in May was the coming-out party for the GPUs. Intel hasn’t provided a clear shipment date for the Flex GPUs… Read more…
August 22, 2022
Amid the high-performance GPU turf tussle between AMD and Nvidia (and soon, Intel), a new, China-based player is emerging: Biren Technology, founded in 2019 and headquartered in Shanghai. At Hot Chips 34, Biren co-founder and president Lingjie Xu and Biren CTO Mike Hong took the (virtual) stage to detail the company’s inaugural product: the Biren BR100 general-purpose GPU (GPGPU). “It is my honor to present… Read more…
August 22, 2022
Amid wildfire and drought season, worries are growing that another natural disaster is looming over the West Coast: megafloods. While concurrent threats from megafloods and droughts may seem at odds with each other, researchers at the National Center for Atmospheric Research (NCAR) recently conducted a supercomputer-powered study showing that climate change is greatly exacerbating the risk of catastrophic flooding in California. Read more…
August 17, 2022
“It is my privilege to welcome you to the dedication of Frontier, the supercomputer that broke the exascale barrier.” That was the introduction by Oak Ridge National Laboratory Director Thomas Zacharia, at a small, public event on August 17 to officially dedicate the supercomputer, which in May became the first system to achieve over 1.0 exaflops of 64-bit performance on the… Read more…
May 11, 2022
Intel has shared more details on a new interconnect that is the foundation of the company’s long-term plan for x86, Arm and RISC-V architectures to co-exist in a single chip package. The semiconductor company is taking a modular approach to chip design with the option for customers to cram computing blocks such as CPUs, GPUs and AI accelerators inside a single chip package. Read more…
May 30, 2022
In April 2018, the U.S. Department of Energy announced plans to procure a trio of exascale supercomputers at a total cost of up to $1.8 billion dollars. Over the ensuing four years, many announcements were made, many deadlines were missed, and a pandemic threw the world into disarray. Now, at long last, HPE and Oak Ridge National Laboratory (ORNL) have announced that the first of those… Read more…
July 19, 2022
The U.S. Senate on Tuesday passed a major hurdle that will open up close to $52 billion in grants for the semiconductor industry to boost manufacturing, supply chain and research and development. U.S. senators voted 64-34 in favor of advancing the CHIPS Act, which sets the stage for the final consideration… Read more…
May 30, 2022
The 59th installment of the Top500 list, issued today from ISC 2022 in Hamburg, Germany, officially marks a new era in supercomputing with the debut of the first-ever exascale system on the list. Frontier, deployed at the Department of Energy’s Oak Ridge National Laboratory, achieved 1.102 exaflops in its fastest High Performance Linpack run, which was completed… Read more…
June 8, 2022
The first-ever appearance of a previously undetectable quantum excitation known as the axial Higgs mode – exciting in its own right – also holds promise for developing and manipulating higher temperature quantum materials… Read more…
June 21, 2022
Additional details of the architecture of the exascale El Capitan supercomputer were disclosed today by Lawrence Livermore National Laboratory’s (LLNL) Terri Read more…
July 1, 2022
HPCwire takes you inside the Frontier datacenter at DOE’s Oak Ridge National Laboratory (ORNL) in Oak Ridge, Tenn., for an interview with Frontier Project Direc Read more…
August 16, 2022
Tesla has revealed that its biggest in-house AI supercomputer – which we wrote about last year – now has a total of 7,360 A100 GPUs, a nearly 28 percent uplift from its previous total of 5,760 GPUs. That’s enough GPU oomph for a top seven spot on the Top500, although the tech company best known for its electric vehicles has not publicly benchmarked the system. If it had, it would… Read more…
June 15, 2022
AMD is getting personal with chips as it sets sail to make products more to the liking of its customers. The chipmaker detailed a modular chip future in which customers can mix and match non-AMD processors in a custom chip package. “We are focused on making it easier to implement chips with more flexibility,” said Mark Papermaster, chief technology officer at AMD during the analyst day meeting late last week. Read more…
May 31, 2022
Intel reiterated it is well on its way to merging its roadmap of high-performance CPUs and GPUs as it shifts over to newer manufacturing processes and packaging technologies in the coming years. The company is merging the CPU and GPU lineups into a chip (codenamed Falcon Shores) which Intel has dubbed an XPU. Falcon Shores… Read more…
June 16, 2022
The long-troubled, hotly anticipated MareNostrum 5 supercomputer finally has a vendor: Atos, which will be supplying a system that includes both Nvidia and Inte Read more…
August 2, 2022
The Universal Chiplet Interconnect Express (UCIe) consortium is moving ahead with its effort to standardize a universal interconnect at the package level. The c Read more…
March 8, 2022
Just a couple of weeks ago, the Indian government promised that it had five HPC systems in the final stages of installation and would launch nine new supercomputers this year. Now, it appears to be making good on that promise: the country’s National Supercomputing Mission (NSM) has announced the deployment of “PARAM Ganga” petascale supercomputer at Indian Institute of Technology (IIT)… Read more…
August 22, 2022
Amid the high-performance GPU turf tussle between AMD and Nvidia (and soon, Intel), a new, China-based player is emerging: Biren Technology, founded in 2019 and headquartered in Shanghai. At Hot Chips 34, Biren co-founder and president Lingjie Xu and Biren CTO Mike Hong took the (virtual) stage to detail the company’s inaugural product: the Biren BR100 general-purpose GPU (GPGPU). “It is my honor to present… Read more…
June 22, 2022
You may recall that efforts proposed in 2020 to remake the National Science Foundation (Endless Frontier Act) have since expanded and morphed into two gigantic bills, the America COMPETES Act in the U.S. House of Representatives and the U.S. Innovation and Competition Act in the U.S. Senate. So far, efforts to reconcile the two pieces of legislation have snagged and recent reports… Read more…
May 10, 2022
Installation has begun on the Aurora supercomputer, Rick Stevens (associate director of Argonne National Laboratory) revealed today during the Intel Vision event keynote taking place in Dallas, Texas, and online. Joining Intel exec Raja Koduri on stage, Stevens confirmed that the Aurora build is underway – a major development for a system that is projected to deliver more… Read more…
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