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Spencer Chin | Oct 10, 2022
The demand for increased bandwidth and security in network infrastructure, led by artificial intelligence (AI) and machine learning (ML) applications, is re-defining borderless networking. This dramatic growth is expanding the transition to 112G PAM4 connectivity beyond cloud data center and telecom service provider switches and routers to enterprise ethernet switching platforms, which is the market for Microchip Technology’s new META-DX2 Ethernet PHY.
The META-DX2 Ethernet PHY integrates 1.6T (terabits per second) of line-rate end-to-end encryption and port aggregation to maintain the most compact footprint in the transition to 112G PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems.
Related: Reliability – A Key Benefit of the New Ethernet
According to Microchip, META-DX2+’s configurable 1.6T datapath architecture outperforms the next near competitors by 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its unique ShiftIO capability. The flexible XpandIO port aggregation capabilities optimize router/switch port utilization when supporting low-rate traffic. Also, the devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services.
By offering a portfolio of footprint-compatible retimer and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).
Related: PAM4 Connectors, Test Software Address High-Speed Signaling
META-DX2+ differentiated capabilities include dual 800 GbE, quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY. Integrated 1.6T MACsec/IPsec engines that offload encryption from packet processors, so systems can more easily scale up to higher bandwidths with end-to-end security. The greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6T gearbox and hitless 2:1 mux modes.
The chip’s XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimized for enterprise platforms A ShiftIO feature combined with a highly configurable integrated crosspoint enables flexible connectivity between external switches, processors, and optics. The chips provide support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications.
Like the META-DX2L retimer, the META-DX2+ PHYs can be used with Microchip’s PolarFire® FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system to help speed designs into production.
Microchip’s second-generation Ethernet PHY SDK for the META-DX2 family lowers development costs with field-proven API libraries and firmware. The SDK supports all META-DX2L and META-DX2+ PHY devices within the product family. Support for the Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extensions are included to enable agnostic support of the META-DX2 PHYs within a wide range of Network Operating Systems (NOS) that support SAI.
The META-DX2+ family is expected to sample during the fourth calendar.
Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected]
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