Computer Chips
The RISC-V is relatively a new chip in town (pronounced Risk Five). The process is the same as programming a computer, except that the instructions are for the chip that powers the computer.
There has never been a free (open-source) instruction set for computer chips before. Big companies had to pay for the instructions on the chip. Now huge orders don't need to pay royalties to the chip manufacturers. This saves millions of dollars and allows for more free trade.
The RISC-V Instruction Set Architecture (ISA), associated specifications, and stakeholder community are all housed under the nonprofit organization RISC-V International.
In addition to convening and leading associated technical, business, industrial, and special interest organizations, more than 3,100 RISC-V members from 70 different countries contribute to and work together to establish the open specifications for RISC-V.
Interesting Engineering (IE) got an opportunity to speak with the RISC-V International CEO Dr. Calista Redmond, CTO Mark Himelstein, and Stephano Cetola, the Director of Technical Programs at RISC-V International.
The wide-ranging interview sheds light on what it means to have an open-source instruction set for the society. And the reasons why everyone should care.
The interview also covers how the RISC-V ISA stacks up to the competition, and how does the non-profit group feel about the meteoric rise of the RISC-V ISA.
Dr. Calista Redmond: RISC-V is ushering in a new wave of innovation and collaboration in the silicon industry. For decades, custom silicon was only attainable for companies with huge design teams and budgets. Today RISC-V is enabling design freedom across every domain and industry, making it possible for companies of all sizes to push the bounds of innovation and have an opportunity to compete.
What’s also impressive is how RISC-V is driving the open era of computing, removing barriers so companies across geographies and industries can collaborate on shared tools and development resources for the benefit of everyone. This open-standard collaboration approach allows companies to innovate faster and seize fast-growth opportunities.
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Stephano Cetola: RISC-V is the most prolific and open Instruction Set Architecture in history. Currently, there are more than 10 Billion RISC-V cores already shipped and growing. The market is steadily witnessing innovation and adoption moving rapidly across all domains. There’s also demand for RISC-V at every performance level and the collaborative ecosystem inherently breeds a shared investment in driving the fastest-growing ecosystem.
Deloitte Global predicts that the market for RISC-V processing cores will double in 2022 from what it was in 2021 and that it will double again in 2023, as the served addressable market available for RISC-V processing cores continues to expand.
RISC-V is everywhere! RISC-V is used in many applications including consumer and IoT, Automotive, Industrial & Medical, telecommunications and mobile, AI and ML, Edge computing HPC and in the data center. While it is most pervasive in smaller microcontrollers, every month new complex chip designs are being released, and we are seeing many new chips capable of running Linux each year.
Dr. Calista Redmond: As an open architecture, RISC-V offers much more flexibility, scalability, and extensibility compared to closed, proprietary ISAs. RISC-V was designed to handle the latest workloads, including AI, ML, HP, and more. Since RISC-V is an extensible ISA, companies can easily implement the minimal instruction set and add on defined extensions and custom extensions to create custom processors for these new and innovative workloads. Furthermore, RISC-V’s shared tools and development resources help companies reduce risk and accelerate time to market.
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Mark Himelstein: Yes. Competition is good for innovation. Again, there is room for multiple architectures. We’re also very excited about many of the heterogeneous implementations. As you have seen in recent years, Arm has made inroads in traditional X86 domains like HPC (Fujitsu) and laptops (Apple). While the lead time to develop products in this arena takes longer than IoT and embedded, many members (including Intel) are working on RISC-V chips that will fuel a new generation of servers and other devices including super scalar, massively parallel ML, and HPC targeted products.
The key to open standards is collaboration alongside the competition. We work with some of the original architects of x86 to help build an ISA that both learns from the past, as well as looks to the future of computation.
Mark Himelstein: We are strong believers that competition breeds innovation. There are great opportunities for both architectures. We compete in a lot of ways. For example, when a product team is designing new products they will often investigate their choices. RISC-V provides a flexible and modular design that allows implementers to innovate in any way they need to for their solution. Traditional architectures and their business models often constrain and charge more for those choices. This makes RISC-V very attractive to implementers. This is evident by the billions of cores already deployed for profit and the robust open-source and commercial software ecosystem supporting those products.
The two main benefits of RISC-V compared to Arm are cost and flexibility. RISC-V has no licensing fees, and there are no limits placed on what the chip designer includes in their design for RISC-V. But the benefits are much more than that. RISC-V gives companies the opportunity to collaborate on a specification, it gives hardware architects the opportunity to collaborate on designs, and it builds a community around all these efforts. Much like the Linux Kernel did in the 90's, RISC-V is changing the way we think about development: this time in hardware rather than software.
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Stephano Cetola: The simple answer is that the instruction set is smaller and simpler in RISC (specifically in RISC-V) than in CISC. However, that simplicity leads to many benefits other than speed. The language (assembly) of RISC-V is easier to understand for programmers than CISC. This translates to compilers being simpler, for example compiling the C language into assembly. The software stack follows from there. Debuggers, code generators, system libraries: all these can be simpler at their base because they are dependent on a simpler underlying "language" in the set of instructions being reduced.
Stephano Cetola: RISC-V was invented by a team of engineers and Ph. D. scholars at UC Berkeley in 2011. However, it takes a whole community of engineers, architects, software developers, and project managers to manage the RISC-V ecosystem. Each year we ratify new extensions to the original Instruction Set Architecture (ISA) and each year our community grows to support these extensions.
Dr. Calista Redmond: Our vision is to bring RISC-V everywhere you can imagine, from cars to data centers, IoT devices, smartphones, supercomputers, and more. With RISC-V already being used for space applications, we’re well on our way to bringing RISC-V to workloads across the full spectrum of computing.
To continue this momentum, we’re working hard to drive progression on RISC-V standards. Last year, we announced the ratification of 15 new architecture extension specifications, and we have more exciting technical milestones to share in the coming months. It is also a key priority for us to continue to grow the RISC-V community and deepen engagement as we work to bring RISC-V everywhere.
Success will be the rapid adoption that we’re already seeing in the industry and around the world. We will measure it in cores spanning a variety of workloads as well as the continued momentum of members engaging in the community. Today we have 3,100+ members, and a 2021 growth of 134 percent with no signs of slowing down. This engagement is essential to ensure strategic investment in RISC-V is well placed, to grow partnerships, to meet new customers, and accelerate technical development.
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Stephano Cetola: As more complex designs become commonplace, we will see RISC-V in even more products, including consumer goods. We are expecting the first RISC-V laptop to ship early next year running Linux, and prototypes for mobile RISC-V applications are already being demoed using the Android operating system.
RISC-V is officially all over the world … and space. Just this month, NASA’s Jet Propulsion Laboratory selected Microchip, in partnership with SiFive, to develop the High-Performance Spaceflight Computing (HPSC) processor. The new HPSC will support spaceflight computers for future space missions, such as planetary exploration to lunar and Mars surface missions.
In the data center, Esperanto showcases its 1,000-Core RISC-V AI accelerator and Alibaba its RISC-V Xuantie processors with four open cloud and edge processors. In a closer look at the automotive market, Andes now has its ISO 26262 Functional Safety ASIL D Dev Process Certification for RISC-V embedded automotive safety with Andes processors, and Renesas and SiFive partnered on next-gen, high-end RISC-V automotive applications. For the AI and ML market, NVIDIA CUDA announced support for Vortex RISC-V GPGPU to enable scaling from 1-core to 32-core GPU based on RV32IMF ISA. This is only a taste of the breadth of the innovative new applications of RISC-V.
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